Back-illuminated imaging devices are known wherein an incident beam such as visible light is irradiated on to a surface (back surface) opposite to a surface (front surface) where electrodes and the like of a chip are arranged (see patent document 1). The back illuminated imaging device is provided with a converting portion for each pixel (for example a photoelectric converting portion if the incident beam is incident light) on the back surface of the chip and on the front surface of the chip is provided a portion (a charge processing portion) that in some manner processes signal charges, examples being an A/D converter and a signal storage portion.
Since the back illuminated imaging device can achieve an aperture ratio of nearly 100%, it is able to offer extremely high sensitivity. Consequently, the back illuminated imaging device is frequently used in applications requiring high sensitivity such as in the fields of astronomy and electron microscopy. Furthermore, back illuminated imaging devices that have high sensitivity are also suited for high speed imaging in which the exposure time for a single image is short.
The present inventors have developed an in-situ storage image sensor (ISIS) provided with linear signal storage portions inside or in the vicinity of pixels (for example, see patent document 2, non-patent document 1, and non-patent document 2). Furthermore, the present inventors have developed a back illuminated imaging device in which a principle of the in-situ storage image sensor is applied (see patent document 3).
FIG. 30 and FIG. 31 show an in-situ storage type back illuminated imaging device. A plurality of pixels 203 are arranged two-dimensionally on an incident surface (back surface) 202 of a back illuminated imaging device 201. For simplification, FIG. 30 shows only 12 (4 lines×3 rows) of the pixels 203, but the number of lines and number of rows of the pixels 203 may be two or more respectively. Furthermore, for simplification, FIG. 30 does not show a photoelectric converting layer 205 and a charge collecting layer 206, which are described later.
As shown in FIG. 31, a p-photoelectric converting layer 205 is provided on the incident surface 202 of a chip 204. And an n-charge collecting layer 206 is provided adjacent to a front surface 208 of the photoelectric converting layer 205. Further still, an n-type input region 209 is provided on the front surface 208 for each of the pixels 203. An n-charge accumulation portion 207 is provided extending from the charge collecting layer 206 to the input region 209 for each of the pixels 203.
A signal storage CCD 211, which extends diagonally downward in FIG. 30, is connected to each of the input regions 209. A CCD (a vertical reading CCD 212) is provided extending in a vertical direction (row direction) in the drawing for each row of the input regions 209. Further still, a drain line 227 is provided adjacent to each of the vertical reading CCDs 212. And further still, a CCD (a horizontal reading CCD 125) is provided extending in a horizontal direction (line direction) in the drawing.
The signal storage CCDs 211 and the vertical reading CCDs 212 are embedded in p-type charge blocking regions 213 that are provided on the front surface of the chip 204. A concentration distribution of p-type impurities in the charge blocking regions 213 is constant. Furthermore, as indicated by symbol T in FIG. 31, the thickness of the charge blocking regions 213 as measured from the front surface 208 of the chip 204 is constant. P+ channel stops 214 are provided between two adjacent signal storage CCDs 211 and between the signal storage CCD 211 and the vertical reading CCD 212. Numeral 215 indicates an electrode for driving the signal storage CCD 211 and numeral 216 indicates an electrode for sending the signal charges from the input region 209 to the signal storage CCD 211.
Electrons (signal charges) produced by the photoelectric converting layer 205, which are caused by irradiation of light onto the incident surface 202 as indicated by arrow A, are moved to the charge collecting layer 206 as indicated by dashed line B. Furthermore, the electrons move horizontally in the charge collecting layer 206 in FIG. 31 and reach the charge accumulation portions 207, then are sent from the input region 209 to the signal storage CCDs 211.
With reference to FIG. 32 also it is evident that the electric potential distribution of the n-charge collecting layer 206 is affected by having the n-type signal storage CCDs 211 and the vertical reading CCDs 21 and the p+ channel stops 214 embedded alternately in the p-type charge blocking regions 213. In more detail, closed regions having low electric potential are produced as indicated by arrow C in FIG. 32. Thus, on dashed line D, where portions having the highest electric potential are linked horizontally (movement direction of electrons), unevenness is produced in the electric potential distribution as shown in FIG. 33. It is necessary for electrons to cross this unevenness in electric potential distribution and move through the charge collecting layer 206. Consequently, due to the unevenness in electric potential distribution, the movement speeds at which the electrons move through the charge collecting layer 206 is lowered. For example, when a gap E in the unevenness of electric potential distribution is 0.3 V or more, some of the electrons become trapped and produce an afterimage when viewed at short time intervals even under room temperature, and therefore the time resolution is reduced. When the diffusion movement speed of the electrons is low, such as in low temperatures, electrons become trapped by unevenness in the electric potential distribution even with lower voltages. Symbol 217 in FIG. 33 conceptually shows electrons trapped in the unevenness of the electric potential distribution. The movement speed of electrons becomes extremely slow by electrons being trapped in the unevenness of the electric potential distribution and therefore afterimages are produced when the time interval between frames is narrowed, thereby reducing the time resolution. Similarly, in high sensitivity imaging where the number of photoelectrons is small such as in the use of electron microscopes, the movement speed of the electrons becomes extremely slow by electrons being trapped in the unevenness of the electric potential distribution and therefore afterimages are produced when the time interval between frames is narrowed, thereby reducing the time resolution.
Due to the presence of unevenness in the electric potential distribution in the charge collecting layer 206, the movement speed of electrons in the charge collecting layer is reduced, which incurs reductions in time resolution, that is, reductions in imaging speed. Consequently, the unevenness in the electric potential distribution in the charge collecting layer 206 presents a serious problem in achieving ultra high sensitivity imaging at ultra high speeds.
[Patent document 1] JP H9-331052 A
[Patent document 2] JP 2001-345441 A
[Patent document 3] JP 2004-235621 A
[Non-patent document 1] Takeharu ETOH et al. “A CCD Image Sensor of 1M frames/s for Continuous Image Capturing of 103 Frames,” Digest of Technical Papers, 2002 IEEE International Solid-State Circuits Conference, 2002, Vol. 45, p. 46 to 47
[Non-patent document 2] Takeharu ETOH and four others: “An In-situ Storage Image Sensor of 1M frames/s with Slanted Linear CCD Storage,” Journal of the Institute of Image Information and Television Engineers, the Institute of Image Information and Television Engineers, 2002, Vol. 56, No. 3, p. 483 to 486.